As well-known in the field of semiconductor packaging, a leadless leadframe is used as a die carrier in a leadless semiconductor package for smaller footprint and lower manufacturing cost. However, after singulation, a leadless semiconductor package still needs to go through final test via individual test socket for the verification of the electrical performance, therefore, the cost of final test cannot be reduced.
In U.S. Pat. No. 6,489,218, a conditional leadless semiconductor package and its manufacturing process flow are revealed. As shown in FIG. 1, the leadless semiconductor package has a leadless leadframe 10. In each unit, the leadless leadframe 10 has a plurality of leads 11 and a chip pad 12. A plated metal layer 13, such as silver, nickel/gold, is deposited on the upper surface of the leads 11 and the chip pad 12 for enhancing connection of bonding wires 30 between the leadless leadframe 10 and a semiconductor chip 20. The semiconductor chip 20 is attached to the chip pad 12, then a plurality of bonding wires 30 connect the leads 11 of the leadless leadframe 10 with the semiconductor chip 20. Thereafter, an encapsulant 40 seals the semiconductor chip 20 and the bonding wires 30. The process flow for manufacturing the leadless semiconductor packages is shown in FIG. 2, including the step 1 of “providing a leadless leadframe with a packaging matrix”, the step 2 of “attaching a plurality of semiconductor chips to the leadless leadframe”, the step 3 of “electrically connecting the semiconductor chips with the leadless leadframe”, the step 4 of “encapsulating the packaging matrix with an encapsulant”, the step 5 “singulating the leadless leadframe”, and the step 6 “electrically testing the singulated leadless semiconductor packages”. First of all, in step 1, a leadless leadframe 10 with a packaging matrix is provided, a plurality of units are arranged in an array in the packaging matrix. Moreover, the plated metal layer 13 is formed on the upper surface of the leadless leadframe 10 including the cutting streets between the units. Thereafter, in step 2, a plurality of semiconductor chips 20 are attached to the chip pads 12, and then, in step 3, a plurality of bonding wires 30 connect the leads 11 of the leadless leadframe 10 with the semiconductor chips 20. Thereafter, in step 4, an encapsulant seals the packaging matrix to cover a plurality of units, which is the precursor of the package bodies 40 before singulation. Next, in step 5, a plurality of individual leadless semiconductor packages are formed by sawing the encapsulant along the cutting streets instead of punching method. In order to saw the encapsulant easily, a metal layer 14 is plated on the lower surface of the leadless leadframe 10 except for the cutting streets. The cutting streets are exposed from the metal layer 14. Therefore, the metal layer 14 is used as an etching mask. After etching the cutting streets, a plurality of package bodies 40 are easily formed by sawing the thinned encapsulant. However, the upper metal layer 13 is also not removed by etching as same as the lower metal layer 14, therefore, the leads 11 electrically connect each other and the leadless semiconductor packages 40 still can not be electrically tested in a matrix of a leadless leadframe before sawing.